SUNNYVALE, Calif., June 10, 2024 — Synopsys (Nasdaq: SNPS) today announced what it said is the industry’s first PCIe 7.0 IP solution consisting of controller, IDE security module, PHY, and verification IP. The company said the offering will enable chip makers to address demanding bandwidth and latency requirements for transferring massive amounts of data for compute-intensive AI […]
PCI-SIG Announces CopprLink Cable Specifications for PCIe 5.0 and 6.0
May 1, 2024 by Leave a Comment
BEAVERTON, Ore. – May 1, 2024 – PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) standard, today announced the release of the CopprLink Internal and External Cable specifications. The CopprLink Cable specifications provide signaling at 32.0 and 64.0 GT/s and leverage well-established industry standard connector form factors maintained by SNIA. “The CopprLink Cable […]
HPC News Bytes 20231120: SC23 Overview – Exascale Update, New AI Chips, Quantum Village, UCIe-PCIe-Ultra Ethernet
November 20, 2023 by
In this edition of the HPC News Bytes podcast, Shahin takes us on a rapid (5:04) tour of SC23, analyzing the key developments and new technologies that highlighted last week’s conference in Denver: Conference attendance expands to 14,000; exascale update and future; raft of new chips, many focused on AI; Quantum Village at SC23; UCIe, PCIe and Ultra Ethernet
PCI-SIG Exploring PCIe over Optical Interconnects
August 2, 2023 by
BEAVERTON, OR. – August 2, 2023 – PCI-SIG today announced the formation of a workgroup to deliver PCI Express (PCIe) technology over optical connections. The PCI-SIG Optical Workgroup intends to be optical technology-agnostic, supporting a range of optical technologies, while potentially developing technology-specific form factors. “Optical connections will be an important advancement for PCIe architecture as they will […]
PCIe 5.0 will supercharge AI at the Edge if it’s done right
November 23, 2022 by Leave a Comment
PCIe Gen 5 is a key technology for driving transportable or edge AI systems to higher performance, especially those with demanding space, environmental or cooling needs. But AI program managers should evaluate their technology suppliers’ Gen 5 implementations to ensure they fully realize the technology’s benefits.
Molex Launches PCIe Cable Connection for Open Compute Project Servers
October 12, 2022 by
LISLE, IL – October 12, 2022 – Molex, a global electronics company, has announced its NearStack PCIe Connector System and Cable Assemblies for next-gen servers. Developed in collaboration with members of the Open Compute Project (OCP), NearStack PCIe replaces traditional paddle-card cable solutions to optimize signal integrity and improve system performance. A feature of NearStack PCIe is […]
How Aerospace/Defense Can Harness Data with a Well-Designed AI Infrastructure
September 12, 2022 by
In this sponsored post, our friends over at Silicon Mechanics discuss how solving mission-critical problems using AI in the aerospace and defense industry is becoming more of a reality. Every day, new technologies emerge that can simplify deployment, management, and scaling of AI infrastructure to ensure long-term ROI. There are several questions to ask yourself to ensure deploying AI workloads, and harnessing the full potential of data, in aerospace/defense is much more plausible and efficient.
TEAMGROUP Claims 1st Heat Dissipating Graphene PCIe 4.0 SSD Label for Cooling Performance
August 16, 2022 by
August 16, 2022, Taipei — Memory company TEAMGROUP announced announced MP44L M.2 PCIe 4.0 SSD, featuring what it said is a breakthrough cooling technology: the industry’s first SSD label to incorporate graphene copper foil. This less than 1mm thick heat dissipating graphene SSD label has received Utility Patents [1] and is adhered to the SSD to provide […]
PCI-SIG Announces PCI Express 7.0 Specification to Reach 128 GT/s
June 21, 2022 by
SANTA CLARA, Calif., June 21, 2022 — PCI-SIG today announced that the PCI Express (PCIe) 7.0 specification will double the data rate to 128 GT/s and is targeted for release to members in 2025. PCI-SIG technical workgroups will be developing the PCIe 7.0 specification with the following feature goals: Delivering 128 GT/s raw bit rate and […]
Fungible Picks Avery Design Systems PCI Express VIP for Hyperscale Compliance, Connectivity
February 28, 2022 by
Tewksbury, MA., Feb 28, 2022 — Avery Design Systems, maker of functional verification solutions, today announced its PCI Express Verification IP (VIP) has been selected by Fungible Inc., a data center infrastructure company, for compliance and connectivity of its Fungible Data Processing Unit (DPU). The Fungible DPU is designed to address requirements in hyperscale data […]
