Along with his article to be found on this site, technology analyst Adrian Cockcroft of OrionX (and former AWS vice president) joins Shahin and Doug after SC23 to discuss TOP500 trends, the AI-HPC crossover, liquid cooling, chiplets, and the emergence of UCIe and CXL – some of the anticipated advancements are truly eye-popping. In this podcast, sponsored by Lenovo, the relentless pursuit of higher performance, the acceleration in the pace of change in high performance processing, is examined.
@HPCpodcast: Tech Analyst Adrian Cockcroft on Trends Driving Future HPC Architectures
November 30, 2023 by
SC23: TOP500 Trends, the AI-HPC Crossover, Chiplet Standardization, the Emergence of UCIe and CXL Advancements
November 29, 2023 by
By Adrian Cockcroft, Partner & Analyst, OrionX Last year the UCIe chiplet standard had just been launched, and since then just about everyone has joined it, about 130 companies. The idea is that to build a complete CPU or GPU you don’t have to put it all on the same chip from the same….
Astera Labs Launches Cloud-Scale Interop Lab for CXL Solutions at Scale
January 31, 2023 by
SANTA CLARA, CA – January 31, 2022 – Astera Labs, maker of connectivity solutions, today announced the expansion of its Cloud-Scale Interop Lab designed to provide robust interoperability testing between its Leo Memory Connectivity Platform and an ecosystem of CXL-based CPUs, memory modules, and operating systems. “Compute Express Link (CXL) is proving to be a […]
Silicon Photonics and the Hunt for an HPC Bandwidth Bottleneck Breakthrough
December 19, 2022 by
[SPONSORED CONTENT] “FLOPS are cheap, moving data is expensive.” In HPC circles this sentiment is heard often. There’s a growing sense that classical HPC systems and the advanced chips that power them are pushing up against their practical limits, that some foundational new technology is needed to build more balanced systems to achieve the next […]
@HPCpodcast: CXL News, the CHIPS Act, Chips and Nm and Chip ‘Sprawl’
August 19, 2022 by
We’ve heard so much about the CXL interconnect – including the recent announcement of CXL v3.0 – and components that are CXL-ready, that it may come as a surprise that CXL v1.1 “hosts” are only just now shipping. It’s a technology that could play a central role in the ever-more heterogenous, more memory-intensive systems of the future. And now, after several years of experimentation and various interconnect consortia, CXL is emerging as the standard for advanced functionality for fabric technologies. Along with CXL we also discuss some of the details of the CHIPS and Science Act….
The Evolution of HPC Storage: More Choices Yields More Decisions
July 19, 2022 by
[SPONSORED CONTENT] The past few years have brought many changes into the HPC storage world, both with technology like non-volatile memory express (NVMe) or persistent memory, and the growth of software defined storage solutions. Gone are the days when IBM Spectrum Scale (secretly, we know we all still call it GPFS) or Lustre were the only real choices in the market. In retrospect, the choice was easy: you picked one of the two and away you went. And nobody ever wondered if they made the right choice.
Astera Labs Claims 1st CXL 2.0 Memory Accelerator SoC Platform
November 15, 2021 by
SANTA CLARA, CA, U.S. – November 15, 2021 – Astera Labs, make of connectivity solutions for intelligent systems, today announced its new Leo Memory Accelerator Platform for Compute Express Link (CXL) 1.1/2.0 interconnects to enable disaggregated memory pooling and expansion for processors, workload accelerators, and smart I/O devices. Leo overcomes processor memory bandwidth bottlenecks and […]
CXL Consortium at SC21: 1st Public Demo of Compute Express Link
November 15, 2021 by
November 15, 2021 – Beaverton, OR – The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, will showcase growing momentum for CXL technology at Supercomputing (SC21), taking place at America’s Center in St. Louis, Missouri and virtually November 15-18. The CXL specification enables a high-speed, efficient interconnect between the CPU and […]
Samsung Claims First Open-source Software for CXL Memory Platform
October 7, 2021 by
Samsung today introduced what it said is the first open-source software solution designed for the Compute Express Link (CXL) memory platform. The company said the Scalable Memory Development Kit (SMDK) builds on Samsung’s May launch of a CXL memory expander, designed to allow memory capacity and bandwidth to scale to levels exceeding server system limits. […]
Tear Down These Walls: How CXL Could Reinvent the Data Center
June 12, 2021 by
The move to heterogenous computing will require shifting some … interconnects to a more performant industry standard interface enabling new capabilities like memory tiers, pooled memory, and even the convergence of memory and storage. And to unshackle architectural innovation and choice, we need an open standard with broad industry acceptance. Enter the Compute Express Link (CXL). CXL is an open interface that standardizes a high-performance interconnect for data-centric platforms – it provides the ability to connect CPUs to XPUs, storage, memory and networking, enabling increased degrees of freedom for platform architecture via the ability to build more optimized infrastructures.
