SANTA CLARA, CA — Aug. 2, 2022 — At the Flash Memory Summit today, Avery Design Systems announced its Verification IP (VIP) for 800Gbps Ethernet can now be used to perform virtual network co-simulation for the full layer Ethernet 2-7 network stack. The combination of the VIP and a virtual co-simulation/co-emulation system enables the running […]
Avery Design Systems Announces 800G Ethernet VIP Virtual Network Co-simulation Platform
August 2, 2022 by
Avery Design Systems Announces Verification Support for New Chiplet Interconnect Standard
June 15, 2022 by
Tewksbury, MA – June 15, 2022 – Avery Design Systems, a functional verification solutions company, today announced its support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity. Avery’s offering includes models and test suites that support […]
Avery Design Systems and Rambus Extend Memory Model and PCIe VIP Collaboration
May 19, 2021 by
Tewksbury, MA. and San Jose – May 19, 2021 – Avery Design Systems, maker of functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of chips and silicon IP designed to make data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to […]
Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio
April 28, 2021 by
Tewksbury, MA., April 28, 2021 — Avery Design Systems, a functional verification solutions company, today announced that Astera Labs, a connectivity solutions for intelligent systems specialist, successfully used Avery’s Compute Express Link (CXL) 2.0 and PCI Express (PCIe) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio. The Avery CXL 2.0 and PCIe […]
