Overarching both themes is the slowing of Moore’s Law, the deceleration of improvement in HPC performance combined with increasing costs for new generations of systems. In addition, implementing and realizing the benefits of new systems is slowing ….
Cadence and Intel Foundry Partner on EMIB Packaging for Heterogeneous Integration
February 21, 2024 by
Feb. 21, 2024 — EDA software company Cadence and Intel Foundry have collaborated to develop an integrated advanced packaging flow utilizing Embedded Multi-die Interconnect Bridge (EMIB) technology to address the complexity in heterogeneously integrated multi-chip(let) architectures, the companies announced. The collaboration enables Intel customers to leverage advanced packaging to accelerate the high-performance computing (HPC), AI […]
@HPCpodcast: Tech Analyst Adrian Cockcroft on Trends Driving Future HPC Architectures
November 30, 2023 by
Along with his article to be found on this site, technology analyst Adrian Cockcroft of OrionX (and former AWS vice president) joins Shahin and Doug after SC23 to discuss TOP500 trends, the AI-HPC crossover, liquid cooling, chiplets, and the emergence of UCIe and CXL – some of the anticipated advancements are truly eye-popping. In this podcast, sponsored by Lenovo, the relentless pursuit of higher performance, the acceleration in the pace of change in high performance processing, is examined.
Gen AI Chip Startup d-Matrix Announces $110M in Series B Funding
September 6, 2023 by
Santa Clara, Calif. – September 6, 2023 – Gerative AI chip startup d-Matrix has closed $110 million in a Series-B funding round led by Singapore-based global investment firm Temasek. The goal of the fundraise is to enable d-Matrix to begin commercializing Corsair, the world’s first Digital-In Memory Compute (DIMC), chiplet-based inference compute platform, after the […]
Avery Design Systems Announces Verification Support for New Chiplet Interconnect Standard
June 15, 2022 by
Tewksbury, MA – June 15, 2022 – Avery Design Systems, a functional verification solutions company, today announced its support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity. Avery’s offering includes models and test suites that support […]
Heavyweight UCIe Consortium Launched to Standardize Chiplet Ecosystem
March 2, 2022 by
A consortium of tech industry heavyweights today announced the Universal Chiplet Interconnect Express (UCIe) industry consortium with a mission to establish a die-to-die interconnect standard and foster an open chiplet ecosystem. Founding members include Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing […]
