Dr. Thomas Theis
The continuing evolution of silicon complementary metal–oxide–semiconductor (CMOS) technology is clearly approaching some important physical limits. Since roughly 2003, the inability to reduce supply voltages according to constant-electric-field scaling rules, combined with economic constraints on power density and total power, has forced designers to limit clock frequencies even as devices have continued to shrink. Still, there is a plausible path to Exascale, based on the continued evolution of silicon device technology, silicon photonics, 3D integration, and more.
“The immediate challenge is to execute. However, longer term research exploring entirely new devices and architectures is essential if we want to take high performance computing well beyond Exascale. Recent years have brought a large increase in research funding and interest in new device concepts. Some of the devices explored to date, such as tunneling field-effect transistors (TFETs) based on III-V semiconductors, promise to open a new low-power design space which is inaccessible to conventional field-effect transistors (FETs). Nanomagnetic devices may allow memory and logic functions to be combined in novel ways. And newer, perhaps more promising device concepts continue to emerge. At the same time, research in new architectures has also grown. Indeed, at the leading edge, researchers are beginning to focus on co-optimization of new devices and new architectures. Despite the growing research investment, the landscape of promising research opportunities outside the “FET devices and circuits box” is still largely unexplored.”
The minimum switching energy dissipation in logic devices used in computing is still improving, but the rate of improvement has slowed. Black diamonds replicate data from Landauer (Nature, 1988), and the dashed line is Landauer’s 1988 extrapolation of the historic trend toward kT (300K) indicated by the dotted line. Triangles and Xs are published values from IBM and Intel, respectively, compiled by Chi-Shuen Lee and Jieying Luo at Stanford University during their Ph.D. thesis research with Prof. H.-S. Philip Wong. Open squares are values from the 2013 International Technology Roadmap for Semiconductors.
Dr. Thomas Theis is Executive Director of CNI and Professor in Electrical Engineering in the Fu Foundation School of Engineering, Arts and Sciences. He received a B.S. degree in physics from Rensselaer Polytechnic Institute in 1972, and M.S. and Ph.D. degrees from Brown University in 1974 and 1978, respectively. A portion of his Ph.D. research was done at the Technical University of Munich, where he completed a postdoctoral year before joining IBM Research in December of 1978.
