In this sponsored post on behalf of Intel, we see that in today’s high-performance computing applications, many different pieces of hardware can perform data-centric functions. With diverse accelerators entering the market, programming for multiple architectures has created significant development barriers for software developers.
SeRC Turns to oneAPI Multi-Chip Programming Model for Accelerated Research
At ISC 2020 Digital, the Swedish e-Science Research Center (SeRC), Stockholm, has announced plans to use Intel’s oneAPI unified programming language by researchers conducting massive simulations powered by CPUs and GPUs. The center said it chose the oneAPI programming model, designed to span CPUs, GPUs, FPGAs and other architectures and silicon, to accelerate compute for research using GROMACS (GROningen MAchine for Chemical Simulations) molecular dynamics software, developed by SeRC and first released in 1991
Podcast: A Shift to Modern C++ Programming Models
In this Code Together podcast, Alice Chan from Intel and Hal Finkel from Argonne National Lab discuss how the industry is uniting to address the need for programming portability and performance across diverse architectures, particularly important with the rise of data-intensive workloads like artificial intelligence and machine learning. “We discuss the important shift to modern C++ programming models, and how the cross-industry oneAPI initiative, and DPC++, bring much-needed portable performance to today’s developers.”
Breaking Boundaries with Data Parallel C++
“There’s a new programming language in town. Called Data Parallel C++ (DPC++), it allows developers to reuse code across diverse hardware targets—CPUs and accelerators—and perform custom tuning for a specific accelerator. DPC++ is part of oneAPI—an Intel-led initiative to create a unified programming model for cross-architecture development. Based on familiar C++ and SYCL, DPC++ is an open alternative to single-architecture proprietary approaches and helps developers create solutions that better meet specialized workload requirements.”
New Intel oneAPI DevCloud makes it easier for coders working from home
Today Intel introduced the oneAPI DevCloud to make it easier and more productive for coders currently working from home. “Developing code at home requires access to compute cycles, the latest software development tools, access across diverse hardware architectures—CPUs, GPUs, and FPGAs, and expanded storage capabilities. Through the new oneAPI DevCloud, Intel aims to provide extended access, capacity and support for oneAPI developers working from home.”
Video: How oneAPI Is Revolutionizing Programming
In this video, academics and industry experts weigh in on the potential of oneAPI, the new, unified software programming model for CPU, GPU, AI, and FPGA accelerators that delivers high compute performance for emerging specialized workloads across diverse compute architectures.
oneAPI: Single Programming Model to Deliver Cross-Architecture Performance
Bill Savage from Intel gave this talk at the Intel HPC Developer Conference. “Learn about oneAPI, the new Intel-led industry initiative to deliver a high-performance unified programming model specification spanning CPU, GPU, FPGA, and other specialized architectures. It includes the Data Parallel C++ cross-architecture language, a set of libraries, and a low-level hardware interface. Intel oneAPI Beta products are also available for developers who want to try out the programming model and influence its evolution.”
Full Roundup: SC19 Booth Tour Videos from insideHPC
Now that SC19 is behind us, it’s time to gather our booth tour videos in one place. Throughout the course of the show, insideHPC talked to dozens of HPC innovators showcasing the very latest in hardware, software, and cooling technologies.
Intel HPC Devcon Keynote: Exascale for Everyone
The convergence of HPC and AI is driving a paradigm shift in computing. Learn about Intel’s software-first strategy to further accelerate this convergence and extend the boundaries of HPC as we know it today. oneAPI will ease application development and accelerate innovation in the xPU era. Intel delivers a diverse mix of scalar, vector, spatial, and matrix architectures deployed in a range of silicon platforms (such as CPUs, GPUs, FPGAs), and specialized accelerators—each being unified by an open, industry-standard programming model. The talk concludes with innovations in a new graphics architecture and the capabilities it will bring to the Argonne exascale system in 2021.