Mark Himelstein, chief technology officer at RISC-V International, joins us to discuss the latest developments with the RISC-V instruction set architecture and its growing community and footprint. Topics include: HPC use cases from sensors to supercomputer, achieving customization without loss of compatibility, AI and its impact on chips and systems, and the question on everyone’s mind: when will we see RISC-V in servers and supercomputers? Himelstein also looks at RISC-V’s design wins, including EuroHPC’s backing of R&D to develop HPC hardware and software based on RISC-V. You may also be interested in Shahin’s conversation with Mark in August 2020 to hear how things have evolved since then.
RISC-V Announces First Specifications of 2022
June 21, 2022 by
Nuremberg, Germany – June 21, 2022 – RISC-V International, the open-design standards organization, announced its first four specification and extension approvals of 2022 – Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specifications, and the RISC-V Zmmul multiply-only extension. The news builds on momentum from 2021, in which 16 […]
Intel Joins RISC-V International
February 7, 2022 by
ZURICH – February 7, 2022 – RISC-V International, the global open hardware standards organization, today announced that Intel Corporation has joined RISC-V International at the premier membership level. “This move demonstrates Intel’s strategic investment in open collaboration and support of the open RISC-V architecture and highlights numerous deep RISC-V member partnerships with Intel,” RISC-V said in its announcement. […]
RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension
February 23, 2021 by
Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions. ZiHintPause is the first extension to be ratified under […]
