We caught up with Phil Murphy, CEO of fabrics technology company Cornelis Networks, which has one of the most interesting vendor histories in the HPC community. Extending back to the 1990s and carrying forward extensive interconnect R&D by both Intel and Cray, Cornelis’s OmniPath is a fabric uniquely well-suited to the increasingly heterogeneous world of […]
Amphenol: 112Gb/s Interconnect with eTopus Products for IP Solutions
September 14, 2021 by
San Jose, Sept. 14, 2021 – Amphenol ICC, the global leader in connector technology, design and manufacturing, and eTopus Technology, a pioneer of ultra-high-speed ADC/DSP-based SerDes for wireline applications including data center, cloud, edge, and 5G base stations, today announced the development of a 112Gb/s interconnect technology built on their products. This combined solution is […]
Tear Down These Walls: How CXL Could Reinvent the Data Center
June 12, 2021 by
The move to heterogenous computing will require shifting some … interconnects to a more performant industry standard interface enabling new capabilities like memory tiers, pooled memory, and even the convergence of memory and storage. And to unshackle architectural innovation and choice, we need an open standard with broad industry acceptance. Enter the Compute Express Link (CXL). CXL is an open interface that standardizes a high-performance interconnect for data-centric platforms – it provides the ability to connect CPUs to XPUs, storage, memory and networking, enabling increased degrees of freedom for platform architecture via the ability to build more optimized infrastructures.
Ayar Labs Demos Terabit Optical Link for Co-Packaged Optics and Chip-to-Chip Connectivity
June 10, 2021 by
SANTA CLARA, Calif. — Ayar Labs announced today that it has successfully demonstrated what is said is the industry’s first terabit per second Wavelength Division Multiplexing (WDM) optical link with its TeraPHY optical I/O chiplet and SuperNova multi-wavelength optical source. The demonstration shows a fully functional TeraPHY chiplet with 8 optical ports running error free […]
Molex Scales Deployments of High-Speed Interconnect for Hyperscale and Data Centers
April 29, 2021 by
LISLE, IL – April 29, 2021 – Molex, a leading global connectivity and electronics solutions provider, is scaling global deployments of its high-speed copper and optical interconnects and modules to help customers better address demands for higher bandwidth. Molex’s broad portfolio of next-generation connectivity solutions leverage the latest advancements in copper and optics to deliver high signal integrity, lower […]
Arm Releases Details on 2 Neoverse Platforms and Mesh Interconnect for HPC, ML
April 27, 2021 by
Arm Holdings this morning released information on two new compute platforms and an interconnect for HPC, machine learning and other workloads introduced last September: The Arm Neoverse V1 platform is a new computing tier for Arm and the first Arm-designed core to support Scalable Vector Extension (SVE), delivering 50 percent more performance for HPC and […]
2020 Predictions from Radio Free HPC
January 16, 2020 by
In this podcast, the Radio Free HPC team lays out their tech predictions for 2020. “Henry predicts that we’ll see a RISC-V based supercomputer on the TOP500 list by the end of 2020 – gutsy call on that. This is a double down on a bet that Dan and Henry have, so he’s reinforcing his position. Dan also sees 2020 as the “Year of the FPGA.”
GigaIO Steps Up with PCIe Gen 4 Interconnect for HPC
July 17, 2019 by
In this video from ISC 2019, Marc Lehrer from GigaIO describes the company’s innovative HPC interconnect technology based on PCIe Gen 4. “For your most demanding workloads, you want time to solution. The GigaIO hyper-performance network breaks the constraints of old architectures, opening up new configuration possibilities that radically reduces system cost and protect your investment by enabling you to easily adopt new compute or business processes.”
Gen-Z Consortium Announces the Public Release of Its Core Specification 1.0
February 13, 2018 by
Today the Gen-Z Consortium released the Gen-Z Core Specification 1.0 on its website. As an open systems interconnect, Gen-Z is designed to provide memory semantic access to data and devices via direct-attached, switched or fabric topologies. “The release of core specification 1.0 today is a significant step towards realization of new architectures and evolution of existing technologies to expand into new roles. Samsung is excited to be a member of the Gen-Z Consortium and is committed towards industry open standards.”
Video: Slim Fly – A Cost Effective Low-Diameter Network Topology
March 25, 2015 by
“We introduce a high-performance cost-effective network topology called Slim Fly that approaches the theoretically optimal network diameter. Slim Fly is based on graphs that approximate the solution to the degree-diameter problem. We analyze Slim Fly and compare it to both traditional and state-of-the-art networks. Our analysis shows that Slim Fly has significant advantages over other topologies in latency, bandwidth, resiliency, cost, and power consumption.”
