CARLSBAD, CA – November 17, 2020 – GigaIO Networks, creators of data center network architecture and connectivity solutions, today announced their new Hydra product line, which the company said is the industry’s first fully managed PCI Express (PCIe) Gen 4.0 Pooling Appliance, a high-performance expansion chassis for the disaggregating and pooling of PCIe accelerator devices. […]
At SC20: GigaIO Launches PCIe 4.0 Accelerator Pooling Appliance for the Composable Data Center
November 17, 2020 by
AMD Rolls out Radeon Pro VII Workstation Graphics Card
May 13, 2020 by
Today announced the AMD Radeon Pro VII workstation graphics card for broadcast and engineering professionals, delivering exceptional graphics and computational performance, as well as innovative features. The new graphics card is designed to power today’s most demanding broadcast and media projects, complex computer aided engineering (CAE) simulations and the development of HPC applications that enable scientific discovery on AMD-powered supercomputers.
Astera Labs lands funding for purpose-built connectivity solutions
April 24, 2020 by
Today Astera Labs announced that it has closed its Series B funding with renowned technology investors including Sutter Hill Ventures, Intel Capital, Avigdor Willenz, and Ron Jankov. This investment round, along with a strategic collaboration with TSMC for manufacturing, positions Astera Labs to rapidly scale production of its Aries Smart Retimer, the world’s first Smart Retimer Portfolio for PCI Express (PCIe) 4.0 and 5.0 solutions, and to accelerate development of additional product lines for Compute Express Link (CXL) solutions. “We are very proud of the significant industry traction for our Aries Smart Retimer Portfolio which has been extensively tested with all major CPU, GPU and PCIe 4.0 endpoints,” said Jitendra Mohan, CEO, Astera Labs. “We look forward to accelerating this momentum by partnering with such a distinguished group of technology and manufacturing heavyweights to develop purpose-built connectivity solutions for data-centric systems.”
Barcelona Supercomputing Centre to Optimize Storage and Data Analysis with PPI4HPC
April 6, 2020 by
The Barcelona Supercomputing Center (BSC) will provide a new storage infrastructure for enhanced data analysis capabilities thanks to the PPI4HPC (Public Procurement of Innovations for High Performance Computing). “The proposed infrastructure includes a disk tier built on all-flash technology and spinning disk drives. It changes the way underlying physical drives are managed, accessed and rebuilt in case of failures in order to minimize the impact to the scientific applications. It is a High-Performance Analytics compute infrastructure to run data analytics operations with the latest Power microprocessors and NVMe PCIe local storage to accelerate the workloads.”
2019: The Year of PCI Express 4.0
March 18, 2019 by
Computer systems are about to get a whole lot faster. This year starting at the high end of the market a transition will begin toward systems based on PCI Express 4.0. The interconnect speed will double to 64GB/sec in a 16 lane connection. Tim Miller, Vice President Strategic Development for One Stop Systems, explores the expected speed and innovation stemming from the introduction of PCI Express 4.0.
Implementing PCIe Gen 4 Expansion
June 21, 2018 by
After a long run for PCI Express (PCIe) Gen 3, Gen 4 is fast becoming the latest de facto standard for general purpose I/O of the modern computer system. “The ability to run PCIe over cable at full performance with complete software transparency has opened up a range of new application possibilities over the past decade for CPU to I/O system re-partitioning with expansion systems uniquely situated to take advantage of the new PCIe Gen 4 bandwidth soon available on servers.”
Mellanox & Cadence Demonstrate PCI Express 4.0 Multi-Lane PHY IP Interoperability
March 15, 2016 by
Today Cadence announced a collaboration with Mellanox Technologies to demonstrate multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC’s 16nm FinFET Plus (16FF+) process. Customers seeking to develop and deploy next-generation green data centers can now use a silicon-proven IP solution from Cadence for immediate integration and fastest market deployment. Cadence and Mellanox are scheduled to demonstrate electrical interoperability for PCIe 4.0 architecture between their respective PHY solutions at the 2016 TSMC Symposium on March 15, 2016 in Santa Clara, California.
