A UK chip startup, VyperCore, says it has come up with a memory management scheme that does a software layer end-around and delivers as much as a 10x throughput improvement for high performance, general-purpose workloads without code modification.
The company’s core insight, as described in a recent EE Times article: move “away from the processor’s traditional view of its memory as being a single linear space. By defining an object-based view of the memory from within the core of the processor, substantial optimizations in execution of existing code can be achieved.”
The company, founded last year, describes its chip as a modified RISC-V processor that remodels hardware memory interfaces in a way that speeds up managed-language software, such as Python and C#, by up to a factor of 10. The company said it can alsoo achieve a >1.5x speedup on software written in older languages, such as C and C++.
VyperCore announced last month it raised £4m in seed funding (see announcement) that will be used to open UK design centers in Cambridge and Bristol and to develop its first generation of accelerated compute silicon.
Vypercore’s CEO, Ed Nutting partnered with University of Bristol Professor David May starting six years ago – around the time it had become widely acknowledge that Moore’s Law had slowed down. “…processor architectures stopped evolving to meet the needs of modern programming languages” Nutting said in the company’s recent funding announcement.
Here’s how Nutting, explained the processor to EE Times: “The innovation is that we’ve taken what’s known as the ‘garbage collector’ algorithm and placed that into a hardware-state machine deep inside the processor, which then takes it out of software. Hence, it removes that element from the processor’s execution time.”
VyperCore CEO Ed Nutting
“Garbage collection” refers to a programming language capability “that frees up memory space allocated to objects no longer needed by a program,” according to EE Times. “This helps overcome memory quota issues to free up a program’s memory.” Shifting that function within the hardware cuts processor cycles, resulting in VyperCore’s claimed performance boost.
Nutting told EE Time there are about seven layers of software “between the hardware and the top layer of software. This is incredibly slow and wastes a lot of processing time.”
The first phase of VyperCore’s R&D has been to focus on application software (as opposed to low-level system software), “where source code compatibility can be maintained across languages (from Python to C/C++),” the company said on its web site. “This will enable deployment of our accelerator card in data centers without developers needing to change their programs. Tweaked versions of popular open-source compilers and runtimes will be made available for early customers to retarget their applications. This is made much easier for us as the RISC-V community is already well underway porting tools to the architecture.”
VyperCore said its first generation hardware is scheduled to sample with partners in its early access program in Q3 2024.
